For those interested in Computer Architecture...

[ygolo]

I had to fix some "bugs" in the micro-architecture before proceeding.
1) I changed opcode to opcode + constant. Making that bus 12 bits, instead of the 4 bits it originally was.
2) Added an 8-bit data-bus from execute unit to fetch/decode unit.

Hopefully, you could follow why I needed to make those changes. I'll leave it as an opportunity to the reader to test their understanding

So now, I'll show what happens on all of the buses, during a few cycles so that you get the gist of what is happening in the micro-architecture, as well.

First cycle:
Curr. PC Bus: 0x00
Instruction Bus:0x8000B
PAC Bus: (Addr:0, Source:0, Target 0)
RAC Bus: (Addr1:0,Source1:0,Target1:1,Addr2:0,Source2:0,Tar get2:0)
MAC Bus: (Addr:0,Source1:0,Target:0)
Op.Code+Constant Bus (OpCode:0x8, Constant: 0X0B)
Data Bus: 0x00
PRD Bus: 0x00
RRD Bus: 0x0000
MRD Bus: 0x00
PWD Bus: 0x00
RWD Bus: 0x0B
MWD Bus: 0x00
New PC Bus: 0x01

Second cycle:
Curr. PC Bus: 0x01
Instruction Bus:0x80101
PAC Bus: (Addr:0, Source:0, Target 0)
RAC Bus: (Addr1:1,Source1:0,Target1:1,Addr2:0,Source2:0,Tar get2:0)
MAC Bus: (Addr:0,Source1:0,Target:0)
Op.Code+Constant Bus (OpCode:0x8, Constant: 0X01)
Data Bus: 0x00
PRD Bus: 0x00
RRD Bus: 0x0000
MRD Bus: 0x00
PWD Bus: 0x00
RWD Bus: 0x01
MWD Bus: 0x00
New PC Bus: 0x02

Third cycle:
Curr. PC Bus: 0x02
Instruction Bus:0x30001
PAC Bus: (Addr:0, Source:0, Target 0)
RAC Bus: (Addr1:0,Source1:1,Target1:1,Addr2:1,Source2:1,Tar get2:0)
MAC Bus: (Addr:0,Source1:0,Target:0)
Op.Code+Constant Bus (OpCode:0x3, Constant: 0X01)
Data Bus: 0x00
PRD Bus: 0x00
RRD Bus: 0x0B01
MRD Bus: 0x00
PWD Bus: 0x00
RWD Bus: 0x0A
MWD Bus: 0x00
New PC Bus: 0x03

Fourth cycle:
Curr. PC Bus: 0x03
Instruction Bus:0xA0000
PAC Bus: (Addr:0, Source:0, Target 0)
RAC Bus: (Addr1:0,Source1:1,Target1:0,Addr2:0,Source2:1,Tar get2:0)
MAC Bus: (Addr:0xA,Source1:0,Target:1)
Op.Code+Constant Bus (OpCode:0xA, Constant: 0X00)
Data Bus: 0x0A
PRD Bus: 0x00
RRD Bus: 0x0A0A
MRD Bus: 0x00
PWD Bus: 0x00
RWD Bus: 0x0A
MWD Bus: 0x0A
New PC Bus: 0x04

Fifth cycle:

Curr. PC Bus: 0x04
Instruction Bus:0xC0000
PAC Bus: (Addr:0, Source:0, Target 1)
RAC Bus: (Addr1:0,Source1:0,Target1:0,Addr2:0,Source2:1,Tar get2:0)
MAC Bus: (Addr:0xA,Source1:0,Target:0)
Op.Code+Constant Bus (OpCode:0xC, Constant: 0X00)
Data Bus: 0x0A
PRD Bus: 0x00
RRD Bus: 0x0A0A
MRD Bus: 0x00
PWD Bus: 0x0A
RWD Bus: 0x0A
MWD Bus: 0x0A
New PC Bus: 0x05

The lines in red represent buses that changed in the current cycle. The lines in green the ones that changed at all.

[millerm277]

@ygolo, very interesting so far, I'll be paying attention to this thread, as I currently do some work for a company that does GaAs chips. (Electrical Engineering Intern)

[ygolo]

I got rather ill today, so there will be a short break on the concrete examples since that takes a bit of concentration.

Though we don't want to go too far down the circuit design/device physics information (inceredibly intersting stuff in its own right), a certain amount needs to be understood before I specify an implimentation to our micro-architecture.

Although there are a lot of cicuit styles, the most popular one for a long-time is CMOS (Complementary Metal Oxide Semiconductor) technology. The reason for the popularity us due to the generally low power dissipation.

For our purposes, we can think of MOS transistors as simple switches. There are two types often refered to as NMOS, and PMOS.

The device physics is interesting and perhaps we can discuss it in another thread. Pictured below is the NMOS version.


Anyway, the MOS transistors are 4-terminal devices. They are called drain, gate, source, and bulk. For out purposes, we can consider the bulk terminals for the NMOS being connected to ground, and the PMOS bulk terminals connected to supply-voltage of the circuit.

What happens is when the appropriate voltage is applied to the gate terminals, the source and drain terminals become electically connected. It is actually more subtle than this, but we can save that for another thread.

So we can think of the NMOS and PMOS transistors in the following way:

When a high voltage is applied to the gate of an NMOS the source and drain become electrically connected.
When a low voltage is applied to the gate of an PMOS the source and drain become electrically connected.

One catch to this is that (due to particular voltage thresholds to keep the transistors on) NMOS's don't pass high-voltages well between drain and source, and PMOS's don't pass low voltages well.

For this reason, both versions need to be used in a complementary way. There is a lot that goes into the design of these circuits (its what I currently do for work) but for now I'll just show a few basic circuits (from which many other circuits can be built.

First is a simpile inverter, which outpurs the inverted sense of the input. A 0 (low-voltage) input and creates a 1 (high-voltage) output, and vice-versa.


Please, see if you can see how the inversion function is implemented by this particular configuration of PMOS and NMOS.
The NMOS transistors have arrows going in to the bulks and/or no bubbles at the gates. The PMOS transistors have arrows going out of the bulk and/or bubbles at the gates.

In order the keep more complex circuits looking less complicated, inverters tend to be replaced with the following symbol.



Another important function (form which all other logical functions can theoretically be built) is a NAND gate.



If a, and b inputs are 1 (high-voltage) them the output is 0 (low-voltage). In all other cases(when the inputs are valid 1's and 0's), the output is 1 (high-voltage).

Please, see if you can see how the NAND function is implemented by this particular configuration.

Again, to make more complicated circuits more readable, the NAND gates are represented in schematics with a symbol like this:


So far, all the basic circuits I've mentioned have had no "memory." In order to make the flip-flops and other memory elements needed, we employ a little bit of positive feedback.

Here is a high-level schematic of a simple D-flip-flop:


The boxes with the lines in the center are called "transmission gates." They are composed of one PMOS and one NMOS in parallel. Notice that the inverted vesion of every signal that goes to transmission gate has the inverted version as well. That is because one is needed for the PMOS and the other for the NMOS.

There are two distiguishable states, "transparent" and "opaque." In the transparent state, the drains and sources are electrically connected. In the opaque state, the drains are elecrically issolated from the sources.

The end result is that the D input passes to the output when the CLK signal transitions from high to low. At all other times, there are positive feedback mechanisms that keep the output at the value it was last.

Please see if you can see this function from the confuguration.
Hint:The flip-flop is actually composed of two "latches." Each with its own set of tranmission gates and and feedback loop that are opaque or transparent based on the level of the clock.

I really suggest you spend some time puzzling out the basic circuits to see how they create the functions describes. I will answer questions if you get stuck. Once done, I dare say, you will have a much more knowledge than even "lay-people" even in other technichal fields (that is other than Electrical/Computer Engineering or Science).

[Bear Warp]

Originally Posted by ygolo

I really suggest you spend some time puzzling out the basic circuits to see how they create the functions describes.

Will do.

[ygolo]

Been a little distracted. Has everyone who's interested puzzled out the circuits?

The inverter and the NAND get should have been real easy.

The flip-flop may have been tricky, but I think the hint should have been enough.

Was sick for most of the week, and there is the meet-up this weekend, but after that, I'll get cranking on explanations again. Just wanted to see if people are still interested.

Not planning too far ahead, but whats left for our little design is the actual circuits (crude-ones) to implement the bus traffic specified earlier. May have one more generic post on memories and multiplexers before that.

After that, I was think of using a more complicated example program that "polls" the switch bank...which would then segue well into the creation of interrupts (and we could go over an abstract implementation of those).

Then I was thinking, we could go over the concepts of "timing" and "clocking" in more detail in order to introduce the motivation for "pipelining." Once we "pipeline" then we can introduce the concepts of "hazards," and various ways to handle them, and to a light intro to "precise interrupts".

Then there are two possible tracks we could follow:
1) Stay focused on the processor and cover things like super-scalar architectures leading to out-of-order execution (where we need to return to precise interrupts) and we revisit precise interrupts. That has a whole bunch of stuff, like the Tomasulo algorithm/instruction scheduling, branch prediction/error recovery, register renaming, and a whole bunch of other stuff. Then there are vector processors (or vector instructions), stream processesors, and heterogeneous processors like CELL, and various GPUs (nVidia's Tesla is the likely candidate). Then there is the VLIW and EPIC type instructions sets as well. After which we can go on to 2) not having to worry about returning to the guts of a processor too often.

2) The other path is to step away from the processor itself for a little, and take a more system level view where we look at work-loads and benchmarking, and deciding what architectural improvements are actually worth doing for particular work-loads, memory hierarchies, caching, paging, segmentation, snooping and directories, etc. We'll Look at virtual-machines, offloading, and parallel processing in a lot of different models (SMP/CMP shared memory vs. message passing), and the various techniques and traps programmers can fall into when using multiple processors. Cover reliability, availability, bandwidth, and latency of clusters. Look at some basic compiler techniques, and evaluate parallelism in general from an abstract perspective. This gives adequate context for understanding the trade-offs we do when we cover the things in path 1). This is my preferred path.

Anyway, someone let me know if their still interested (breaks have a way of making people lose interest). It does take me some time, so I'd rather not post to the void.

[Athenian200]

Originally Posted by ygolo

I got rather ill today, so there will be a short break on the concrete examples since that takes a bit of concentration.

Though we don't want to go too far down the circuit design/device physics information (inceredibly intersting stuff in its own right), a certain amount needs to be understood before I specify an implimentation to our micro-architecture.

Although there are a lot of cicuit styles, the most popular one for a long-time is CMOS (Complementary Metal Oxide Semiconductor) technology. The reason for the popularity us due to the generally low power dissipation.

For our purposes, we can think of MOS transistors as simple switches. There are two types often refered to as NMOS, and PMOS.

The device physics is interesting and perhaps we can discuss it in another thread. Pictured below is the NMOS version.


Anyway, the MOS transistors are 4-terminal devices. They are called drain, gate, source, and bulk. For out purposes, we can consider the bulk terminals for the NMOS being connected to ground, and the PMOS bulk terminals connected to supply-voltage of the circuit.

What happens is when the appropriate voltage is applied to the gate terminals, the source and drain terminals become electically connected. It is actually more subtle than this, but we can save that for another thread.

So we can think of the NMOS and PMOS transistors in the following way:

When a high voltage is applied to the gate of an NMOS the source and drain become electrically connected.
When a low voltage is applied to the gate of an PMOS the source and drain become electrically connected.

One catch to this is that (due to particular voltage thresholds to keep the transistors on) NMOS's don't pass high-voltages well between drain and source, and PMOS's don't pass low voltages well.

For this reason, both versions need to be used in a complementary way. There is a lot that goes into the design of these circuits (its what I currently do for work) but for now I'll just show a few basic circuits (from which many other circuits can be built.

My first thought when reading this was, "Why do they need to have two kinds of gates that work in precisely opposite ways, instead of just one that can work either way?" But then I realized that they might need to do that because if they didn't, the state of the gate would be the same under either high or low voltage conditions, and would not have any effect on the circuit. Is that it?

First is a simpile inverter, which outpurs the inverted sense of the input. A 0 (low-voltage) input and creates a 1 (high-voltage) output, and vice-versa.


Please, see if you can see how the inversion function is implemented by this particular configuration of PMOS and NMOS.
The NMOS transistors have arrows going in to the bulks and/or no bubbles at the gates. The PMOS transistors have arrows going out of the bulk and/or bubbles at the gates.

The bulk just means the main part of the circuit, right? And the NMOS doesn't need bubbles because it's already connected to ground, but PMOS does because it's connected to the voltage? I'm guessing, here.

In order the keep more complex circuits looking less complicated, inverters tend to be replaced with the following symbol.

It looks like the the same idea as represented by the inversion circuit preceding it symbolically, but without the details of how it works.

Another important function (form which all other logical functions can theoretically be built) is a NAND gate.

If a, and b inputs are 1 (high-voltage) them the output is 0 (low-voltage). In all other cases(when the inputs are valid 1's and 0's), the output is 1 (high-voltage).

Please, see if you can see how the NAND function is implemented by this particular configuration.

All I can see is that somehow or other, Q3 takes the voltage-state of Input A into the circuit, Q4 takes the voltage-state of Input B into the circuit, and then their states are compared with what I assume are some kind of static positive voltage references in Q1 and Q2, which if met result in the current that normally causes the circuit to read as on being blocked/stifled. Is that it?

Abstractly, the idea of an NAND gate seems to be similar to this:

If both conditions A and B are true, this statement is false. Otherwise, this statement is true.

So... is this thing attempting to implement logic in the form of an electronic circuit?

Again, to make more complicated circuits more readable, the NAND gates are represented in schematics with a symbol like this:

It appears to be a representation of how the circuit works on an abstract level (two inputs and one output, with a body doing something with it), but without the details of how it works. It looks like a straightforward representation of it if you already know how it works.

So far, all the basic circuits I've mentioned have had no "memory." In order to make the flip-flops and other memory elements needed, we employ a little bit of positive feedback.

Here is a high-level schematic of a simple D-flip-flop:

The boxes with the lines in the center are called "transmission gates." They are composed of one PMOS and one NMOS in parallel. Notice that the inverted vesion of every signal that goes to transmission gate has the inverted version as well. That is because one is needed for the PMOS and the other for the NMOS.

There are two distiguishable states, "transparent" and "opaque." In the transparent state, the drains and sources are electrically connected. In the opaque state, the drains are elecrically issolated from the sources.

The end result is that the D input passes to the output when the CLK signal transitions from high to low. At all other times, there are positive feedback mechanisms that keep the output at the value it was last.

Please see if you can see this function from the confuguration.
Hint:The flip-flop is actually composed of two "latches." Each with its own set of tranmission gates and and feedback loop that are opaque or transparent based on the level of the clock.

I really suggest you spend some time puzzling out the basic circuits to see how they create the functions describes. I will answer questions if you get stuck. Once done, I dare say, you will have a much more knowledge than even "lay-people" even in other technichal fields (that is other than Electrical/Computer Engineering or Science).

I'm not sure I understand this exactly, but here's what it seems to be doing. If the blue lines are one state of the clock, and the red lines are the other... it seems as if the circuit is set up so that depending on which state the clock is in (red or blue), one part of whatever it is that started at D goes through to the end (and something happens to it) while the other is held in a loop of some kind. What goes through, and what is kept in a loop, seems to alternate between whether red or blue is the current state of the clock. Does it have something to do with volatile memory needing to be constantly self-refreshed in order to avoid being wiped out? Anyway, if the clock cycles frequently, it seems as if the circuit is set up so that all the stuff coming in at D can go through eventually, but ensures that only one thing at a time can do so.

I'm sorry I haven't been commenting as you've been writing... I tend to absorb passively, keep my thoughts to myself. I had some thoughts on your earlier posts, but I wasn't sure anyone would be interested. When I figured out that you were losing motivation because no one was commenting on it, I decided I should share some of my thoughts.

[Bear Warp]

I'm still interested, ygolo. I've just been distracted with college stuff lately. I have plenty of time to look over your last two posts today, though.

Just let me get some coffee first...

[Bear Warp]

(Noob) Questions!

What's Vdd?

What exactly are the drain, gate, source and bulk terminals?

What are bubbles?

[ygolo]

Originally Posted by Athenian200

My first thought when reading this was, "Why do they need to have two kinds of gates that work in precisely opposite ways, instead of just one that can work either way?" But then I realized that they might need to do that because if they didn't, the state of the gate would be the same under either high or low voltage conditions, and would not have any effect on the circuit. Is that it?

The reason they need two kinds of transistors is because the NMOS is not able to transfer the logic 1 from drain to source faithfully, it drops the voltage level by a threshold voltage (the voltage needed to keep the transistor on). The PMOS transistor, however, cannot transfer a logic 0 faithfully. It transfers a voltage that is a threshold voltage above ground.

Originally Posted by Athenian200

The bulk just means the main part of the circuit, right? And the NMOS doesn't need bubbles because it's already connected to ground, but PMOS does because it's connected to the voltage? I'm guessing, here.

The bulk terminal is what is connected to "the substrate" or "the well" of the transistor. The device physics is interesting, but going too far down that path will lead us well off topic. For now, just think of it as a terminal you have to always connect to ground on an NMOS, and to the Voltage supply (usually called Vdd by convention) for PMOS.

On the circuit diagrams, they are the arrows on the transistors on the middle. In many symbols of transistors, the bulk is actually omitted, and you are to infer that the connections are as they should be.

The bubble usually indicates an inversion of the signal connected to it before getting to the device. However, in many symbols of PMOS transistors the bubble is omitted. That is actually a bit annoying to me, but it is done. The conventions are weird. Sometimes they don't really make sense, but once the convention is learned, it doesn't matter too much.

Transistor symbols tend to change a lot. The most proper symbol of an enhancement mode (meaning the applied voltage enhances the conductance of the channel) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are like the ones given in the inverter, but the second vertical line is split into three segments.

Again, there is a lot that can be said about FETs and differences between them. But as long as you can identify NMOS and PMOS in a standard CMOS circuit, we will assume they are enhancement mode (don't worry if this distinction is not understood right now), that should be enough to procede for our purposes.

The inverter works because when the input is a logic 1 (a high voltage), then the NMOS transistor on the bottom pulls the output node down to ground (a logic 0). But if the input is a logic 0 (a low voltage) then the PMOS transistor on the top pulls the output node to Vdd (a logic 1).

Originally Posted by Athenian200

It looks like the the same idea as represented by the inversion circuit preceding it symbolically, but without the details of how it works.

Yup. That is the idea.

Originally Posted by Athenian200

All I can see is that somehow or other, Q3 takes the voltage-state of Input A into the circuit, Q4 takes the voltage-state of Input B into the circuit, and then their states are compared with what I assume are some kind of static positive voltage references in Q1 and Q2, which if met result in the current that normally causes the circuit to read as on being blocked/stifled. Is that it?

Not quite. For digital CMOS circuits like these you don't need to worry about references or voltage comparisons (very much). Just treat the transistors like switches.

Here are a couple of things to note:
In order to connect the output node to ground, you need both Q3 and Q4 to connect their respective drains to their sources. So you need both their inputs to be logic 1s.
In order to connect the output node to Vdd, either Q1 or Q2 or both to connect their respective drains to their sources. This happens when either (or both) of their inputs are logic 0s.

Originally Posted by Athenian200

Abstractly, the idea of an NAND gate seems to be similar to this:

If both conditions A and B are true, this statement is false. Otherwise, this statement is true.

That's the idea. Yes.

Originally Posted by Athenian200

So... is this thing attempting to implement logic in the form of an electronic circuit?

Yup. Until other means of computing become efficient, the logic is implemented electronically.

The thing about the NAND gate is that it is a "logically complete" set of gates by itself. That means you can implement all possible logical functions by just using 2 input NAND gates. You can make it into an inverter by connecting the inputs together and/or connecting one of the inputs to 1. You can create an AND function by inverting the output of the NAND gate(using the NAND as inverter). You can get an OR gate by inverting the inputs(using the NAND as inverter) to a NAND gate.

Originally Posted by Athenian200

It appears to be a representation of how the circuit works on an abstract level (two inputs and one output, with a body doing something with it), but without the details of how it works. It looks like a straightforward representation of it if you already know how it works.

Yes. Circuits can look really complicated without the use of symbols. Generally, we use a box with the inputs and outputs, with none of the internals as a symbol for generic circuits. So we'd have to actually look at the schematic for the symbol to understand what is going on. For standard circuits, like the inverter, NAND and others, there are standard sysmbols, so we don't use a box.

Originally Posted by Athenian200

I'm not sure I understand this exactly, but here's what it seems to be doing. If the blue lines are one state of the clock, and the red lines are the other... it seems as if the circuit is set up so that depending on which state the clock is in (red or blue), one part of whatever it is that started at D goes through to the end (and something happens to it) while the other is held in a loop of some kind. What goes through, and what is kept in a loop, seems to alternate between whether red or blue is the current state of the clock.

That is basically it (though it is more black vs. colored rather than red vs. blue). Can you see why what was on D gets transfered to the red transmission gate when the CL is low, and then transferred from the red transmission gate to the Q node when the CL is high?

Originally Posted by Athenian200

Does it have something to do with volatile memory needing to be constantly self-refreshed in order to avoid being wiped out?

It is volatile memory. But it is a "static" type. The feed-back loops in the latches keep the values stored (as long ad the circuit has power) even where there is no external circuit driving the D-input.
Refreshes (and "pre-charges") are usually associated with "dynamic" circuits, because in these the logic values are stored capacitively, not with the use of a static feedback loop.
This is also interesting stuff. But more in the realm of circuit design.

Originally Posted by Athenian200

Anyway, if the clock cycles frequently, it seems as if the circuit is set up so that all the stuff coming in at D can go through eventually, but ensures that only one thing at a time can do so.

That is the essential idea. The clock cycles on a periodic basis, and these flip-flops will be used in various parts of a circuit to synchronize other signals to the clock.

Originally Posted by Athenian200

I'm sorry I haven't been commenting as you've been writing... I tend to absorb passively, keep my thoughts to myself. I had some thoughts on your earlier posts, but I wasn't sure anyone would be interested. When I figured out that you were losing motivation because no one was commenting on it, I decided I should share some of my thoughts.

I like it when people make comments, that way I know where I am loosing people.

Originally Posted by Bear Warp

I'm still interested, ygolo. I've just been distracted with college stuff lately. I have plenty of time to look over your last two posts today, though.

Just let me get some coffee first...

That's cool. Hopefully, my responses to Athenian will help you as well.
I just wasn't sure since I was sick for a while, if people had just moved on.

[ygolo]

Originally Posted by Bear Warp

(Noob) Questions!

What's Vdd?

What exactly are the drain, gate, source and bulk terminals?

What are bubbles?

Vdd is the conventional name for the power supply. The bubbles are the little circles on the diagrams (on the symbols for the PMOS in the inverter, the symbol for the inverter, and the symbol for the NAND)--they usually indicate an inversion.


Drain is marked by d, or D, source with S or s, Gate with G or g, and Bulk is marked by B, b or unmarked or completely omitted in the diagrams provided.

So (again on a very high level) , what is happening in a transistor is that when a certain voltage is applied to the gate, the source and the drain get connected electrically.

Are you asking for more specifics of transistor operation?