I'll post the image again for reference:
What happens is when CLK is high, CL# (my notation for CL with the bar over it) is low, and in-turn CL is high (note the use of inverters). The opposite happens when CLK is low.
Ignoring the small time delays, CLK is always the same level as CL which is always the opposite level of CL#.
A transmission gate (all the boxes here are transmission gates) is set-up so that when the signal connected to the top is high (and to the bottom low), the left and right sides are connected.
I'll let you try and puzzle it out from there since you seem really close.