So I decided I am going to do smaller chunks than initially thought because there is a lot of writing I am doing.
More “Basic” Circuits
Puzzling out circuits earlier was not just for the purposes of understanding those circuits, but because I am about to hit you with A LOT of circuits, and they should be relatively easy to follow now.
So there are other logic gates that are often used besides the 2-input NAND and the inverter.
There are multiple input NAND gates which use the same symbol as the 2 input NAND gate but more inputs feeding the gate. The logical function outputs a logic 1 in all cases except when all the inputs are a logic 1 (and in this case the output is a logic 0).
Here is an 8-input NAND gate:
If you remove the bubble from the NAND symbol, you get an AND gate. The logical function of AND gates are to output a logic 0 in all cases except when the inputs are all logical1s (in this case the output is a logical 1).
Here is the symbol for an 8-input AND gate.
An AND gate is constructed by adding an inverter to the output of a NAND gate.
Another common function is a NOR gate. The function of a NOR gate is to output a logic 0 if ANY of the inputs is a logic 1, and only output a logic 1 if all the inputs are logic 0.
A two input NOR Gate is constructed in the following manner.
The symbol for a 2 in put NOR is:
Multiple input NOR gates have similar symbols:
An 8-input NOR gate:
Invert the output of a NOR gate and you get an OR gate. The output of an OR gate is a logic 1 if and only if at least on of its inputs is a logic 1. Otherwise, if all the inputs are logic 0, then the output is a logic 0.
Here is an 8-input OR gate:
Multiple Input NAND Gates and NOR gates
Earlier, we saw how to implement 2 input NAND abd NOR gates directly from transistors. You can make higher inputs NAND and NOr gates in a similar fashion. Simply add more NMOS in series and more PMOS in parallel for NAND gates or NMOS in parallel and PMOS is series for NOR gates.
Hopefully, you can see how this works logically. However, the gates cannot get very large because of the increase in output node capacitance (from the PMOS drains, even if many are shared), and pull-down resistance (each NMOS has a small resistance that adds up).
But there is another logical trick to be used to make higher input NAND and NOR gates from lower input ones.
In the NAND case, you simply take the output of a NAND with x inputs send it through an inverter to one of the inputs of a 2-input NAND gate, then take the remaining in put and send it to the other input of a 2-input NAND. Now you have a NAND gate with x+1 inputs. This is a logically correct construction because the first input to the 2-input NAND is only a logic 1 if all the inputs to the NAND with x inputs is a logic 1 (and 0 other wise). Also, the output of the 2-input NAND is only a logic 0 if both its inputs are logic 1. So we can see that the only way this configuration will output a logic 0 is if all the inputs are a logic 1. Otherwise, one of the two inputs to the 2-input NAND gate will be 0, and therefore the output will be a logic 1.
A similar construction works for larger NOR gates. Simply feed the output of a smaller NOR through an inverter to a 2-input NOR that gets the last input.
Various Ways to Describe/Specify General Logic Functions
Hopefully, in the constructions given above it was intuitive to see how the particular functions were built up, and what they were specified to do.
However, in many cases, a more rigorous and organized approach is needed.
Truth Tables
One very brute force, but rather effective way to specify a logical function is through what is known as a truth table. This is simply an enumeration of all possible input combination with a specification of what the output should be.
The truth table for a 3-intput NAND is:
A B C|Out
0 0 0|1
0 0 1|1
0 1 0|1
0 1 1|1
1 0 0|1
1 0 1|1
1 1 0|1
1 1 1|0
Boolean Equations
Generally more compactly we can specify a function through a Boolean Equation.
They will look something like: Y=A#*B+C. Where A# means the inverted version, otherwise known as the “compliment” of A. The “*” indicates and AND of what is on the left and the right. While a + indicates an OR of what is on the left and the right.
Generally, the order of operations is to do all # first, then all *, then all +.
Parentheses can change the order.
Y=A#*B+C is the same as saying Y=(A#*B)+C. However, Y=A#*(B+C) is different.
The “=” can be used in subtly different ways. It can be that a particular signal is defined a particular way. Or it can mean that what is on both sides are logically equivalent.
Manipulating the boolean equations should be rather straight forward once you understand what they are. Seeing a direct implementation using logic gates should be just as easy.
See if you can see that the following are true (use truth-tables if needed), and at the same time see if you can see the circuits each side of the equation would yield directly:
A*0=0
A+1=1
A#+A=1
A#*A=0
A##=A
A*B=B*A
A+B=B+A
A*A=A
A+A=A
A*(B*C)=(A*B)*C
A+(B+C)=(A+B)+C
A*(B+C)=A*B+A*C
A+B*C=(A+B)(A+C)
(A+B)#=A#*B#
(A*B)#=A#+B#