[Athenian200]

Originally Posted by ygolo

The two transistor types is a way to make sure that logic 1's are always Vdd (unless you chose to do it differently, but that we'll save for later), while logic 0 is always ground. In engineering in general, we leave a lot of assumption in the wake of the design process. Because of this we have to make sure these assumptions are met reasonably well. In CMOS circuit design, we are assuming voltages of Vdd or ground for the inputs, so we make sure the outputs reach those levels too (there is a concept of Noise Margining we can get to later, if it becomes relevant).

That's an interesting explanation of how a processor distinguishes 1 from 0 meaningfully... I always wondered how it did that.

Gate leakage is a different issue. As process technology has made the gate Oxide (the "O" in MOS) thinner, leading to more tunneling (you know, the quantum kind--actually 2 kinds, but I digress) producing current through the oxide (which is located under the gate).

That would screw up the whole circuit. It looks like they don't know how to account for the quantum level yet, or if they can compensate for what happens there.

In theory you can make ALL the logic functions including the Pentium instructions and math co-processors with 2 input CMOS NAND gates. However, that is not done because we can actually make things much faster with other techniques.

But if someone were trying to make a processor with the bare minimum of components, that might be done? In other words, if space and component cost became the primary issue instead of speed?

I'll post the image again for reference:


What happens is when CLK is high, CL# (my notation for CL with the bar over it) is low, and in-turn CL is high (note the use of inverters). The opposite happens when CLK is low.

Ignoring the small time delays, CLK is always the same level as CL which is always the opposite level of CL#.

A transmission gate (all the boxes here are transmission gates) is set-up so that when the signal connected to the top is high (and to the bottom low), the left and right sides are connected.

I'll let you try and puzzle it out from there since you seem really close.

Ah, that's what I was missing. The black ones with vertical lines allow pass-through when CL# is high and CL is low (one state of the clock cycle), and the ones with horizontal colored lines allow pass-through when CL# is low and CL is high. When one is in the opposite state, the inverters hold it in the feedback loop until the clock cycles.

I see you Ni is working well. You've anticipated what I wanted to talk about a in a few posts. There is a fundamental limit to how fast you can cycle the clock without resorting to other techniques (of which pipelining is most natural). These other techniques tend to take up yet more and more power.

I won't really be going into the heat generation, since that is quite off-tangent, and it is proportional to the power consumption anyway, which is fairly readily understood in terms of current (and our voltage supply).

Yeah, it looks like we might be reaching the point where more speed is no longer worth the power cost.