[ygolo]

Originally Posted by Athenian200

Ah, so using two transistors is the way they work around the problem of the threshold voltage leakage? Is this the same "gate leakage" I hear talked about so much in connection with processor reviews?

The two transistor types is a way to make sure that logic 1's are always Vdd (unless you chose to do it differently, but that we'll save for later), while logic 0 is always ground. In engineering in general, we leave a lot of assumption in the wake of the design process. Because of this we have to make sure these assumptions are met reasonably well. In CMOS circuit design, we are assuming voltages of Vdd or ground for the inputs, so we make sure the outputs reach those levels too (there is a concept of Noise Margining we can get to later, if it becomes relevant).

Gate leakage is a different issue. As process technology has made the gate Oxide (the "O" in MOS) thinner, leading to more tunneling (you know, the quantum kind--actually 2 kinds, but I digress) producing current through the oxide (which is located under the gate).

Originally Posted by Athenian200

Wow. Come to think of it, I can almost imagine all the early x86 instructions being implemented in this way, if the person were creative enough with circuit design to get the logic to work out from a combination of these (explains why there were so many NTs in that field). That is, prior to Pentium class machines or possibly the advent of math co-processors. I bet it got complicated then. I'm still impressed that someone could implement logic in the form of a physical device. It makes one question the idea that human reasoning is irreducibly complex (You can ignore this, I know it's a bit off topic).

In theory you can make ALL the logic functions including the Pentium instructions and math co-processors with 2 input CMOS NAND gates. However, that is not done because we can actually make things much faster with other techniques.

Originally Posted by Athenian200

Because... for some reason or other, the value can go through the first inverter positioned between the red and blue transmission gates when CL is low, and then can go through another one positioned later in the circuit (but in a similar yet opposite position) when CL is high?

I'll post the image again for reference:


What happens is when CLK is high, CL# (my notation for CL with the bar over it) is low, and in-turn CL is high (note the use of inverters). The opposite happens when CLK is low.

Ignoring the small time delays, CLK is always the same level as CL which is always the opposite level of CL#.

A transmission gate (all the boxes here are transmission gates) is set-up so that when the signal connected to the top is high (and to the bottom low), the left and right sides are connected.

I'll let you try and puzzle it out from there since you seem really close.

Originally Posted by Athenian200

Aha. That explains some of the limitations of circuit design, and why speeding up the "clock" is the easiest way to speed up a processor, but also causes it to generate more heat/friction.

I see you Ni is working well. You've anticipated what I wanted to talk about a in a few posts. There is a fundamental limit to how fast you can cycle the clock without resorting to other techniques (of which pipelining is most natural). These other techniques tend to take up yet more and more power.

I won't really be going into the heat generation, since that is quite off-tangent, and it is proportional to the power consumption anyway, which is fairly readily understood in terms of current (and our voltage supply).