[Athenian200]

Originally Posted by ygolo

The reason they need two kinds of transistors is because the NMOS is not able to transfer the logic 1 from drain to source faithfully, it drops the voltage level by a threshold voltage (the voltage needed to keep the transistor on). The PMOS transistor, however, cannot transfer a logic 0 faithfully. It transfers a voltage that is a threshold voltage above ground.

Ah, so using two transistors is the way they work around the problem of the threshold voltage leakage? Is this the same "gate leakage" I hear talked about so much in connection with processor reviews?

Again, there is a lot that can be said about FETs and differences between them. But as long as you can identify NMOS and PMOS in a standard CMOS circuit, we will assume they are enhancement mode (don't worry if this distinction is not understood right now), that should be enough to procede for our purposes.

Yes, there's quite a bit to learn, I imagine.

The inverter works because when the input is a logic 1 (a high voltage), then the NMOS transistor on the bottom pulls the output node down to ground (a logic 0). But if the input is a logic 0 (a low voltage) then the PMOS transistor on the top pulls the output node to Vdd (a logic 1).

That seems to be exactly how inversion should work.

Not quite. For digital CMOS circuits like these you don't need to worry about references or voltage comparisons (very much). Just treat the transistors like switches.

Here are a couple of things to note:
In order to connect the output node to ground, you need both Q3 and Q4 to connect their respective drains to their sources. So you need both their inputs to be logic 1s.
In order to connect the output node to Vdd, either Q1 or Q2 or both to connect their respective drains to their sources. This happens when either (or both) of their inputs are logic 0s.

Oh. So it's about circuits being completed, or not being completed under certain conditions. That's actually simpler. And I think I knew what it was doing on a higher level, so I probably have it now.

Yup. Until other means of computing become efficient, the logic is implemented electronically.

The thing about the NAND gate is that it is a "logically complete" set of gates by itself. That means you can implement all possible logical functions by just using 2 input NAND gates. You can make it into an inverter by connecting the inputs together and/or connecting one of the inputs to 1. You can create an AND function by inverting the output of the NAND gate(using the NAND as inverter). You can get an OR gate by inverting the inputs(using the NAND as inverter) to a NAND gate.

Wow. Come to think of it, I can almost imagine all the early x86 instructions being implemented in this way, if the person were creative enough with circuit design to get the logic to work out from a combination of these (explains why there were so many NTs in that field). That is, prior to Pentium class machines or possibly the advent of math co-processors. I bet it got complicated then. I'm still impressed that someone could implement logic in the form of a physical device. It makes one question the idea that human reasoning is irreducibly complex (You can ignore this, I know it's a bit off topic).

That is basically it (though it is more black vs. colored rather than red vs. blue). Can you see why what was on D gets transfered to the red transmission gate when the CL is low, and then transferred from the red transmission gate to the Q node when the CL is high?

Because... for some reason or other, the value can go through the first inverter positioned between the red and blue transmission gates when CL is low, and then can go through another one positioned later in the circuit (but in a similar yet opposite position) when CL is high?

It is volatile memory. But it is a "static" type. The feed-back loops in the latches keep the values stored (as long ad the circuit has power) even where there is no external circuit driving the D-input.
Refreshes (and "pre-charges") are usually associated with "dynamic" circuits, because in these the logic values are stored capacitively, not with the use of a static feedback loop.
This is also interesting stuff. But more in the realm of circuit design.


That is the essential idea. The clock cycles on a periodic basis, and these flip-flops will be used in various parts of a circuit to synchronize other signals to the clock.

Aha. That explains some of the limitations of circuit design, and why speeding up the "clock" is the easiest way to speed up a processor, but also causes it to generate more heat/friction.