[ygolo]

Originally Posted by Athenian200

My first thought when reading this was, "Why do they need to have two kinds of gates that work in precisely opposite ways, instead of just one that can work either way?" But then I realized that they might need to do that because if they didn't, the state of the gate would be the same under either high or low voltage conditions, and would not have any effect on the circuit. Is that it?

The reason they need two kinds of transistors is because the NMOS is not able to transfer the logic 1 from drain to source faithfully, it drops the voltage level by a threshold voltage (the voltage needed to keep the transistor on). The PMOS transistor, however, cannot transfer a logic 0 faithfully. It transfers a voltage that is a threshold voltage above ground.

Originally Posted by Athenian200

The bulk just means the main part of the circuit, right? And the NMOS doesn't need bubbles because it's already connected to ground, but PMOS does because it's connected to the voltage? I'm guessing, here.

The bulk terminal is what is connected to "the substrate" or "the well" of the transistor. The device physics is interesting, but going too far down that path will lead us well off topic. For now, just think of it as a terminal you have to always connect to ground on an NMOS, and to the Voltage supply (usually called Vdd by convention) for PMOS.

On the circuit diagrams, they are the arrows on the transistors on the middle. In many symbols of transistors, the bulk is actually omitted, and you are to infer that the connections are as they should be.

The bubble usually indicates an inversion of the signal connected to it before getting to the device. However, in many symbols of PMOS transistors the bubble is omitted. That is actually a bit annoying to me, but it is done. The conventions are weird. Sometimes they don't really make sense, but once the convention is learned, it doesn't matter too much.

Transistor symbols tend to change a lot. The most proper symbol of an enhancement mode (meaning the applied voltage enhances the conductance of the channel) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are like the ones given in the inverter, but the second vertical line is split into three segments.

Again, there is a lot that can be said about FETs and differences between them. But as long as you can identify NMOS and PMOS in a standard CMOS circuit, we will assume they are enhancement mode (don't worry if this distinction is not understood right now), that should be enough to procede for our purposes.

The inverter works because when the input is a logic 1 (a high voltage), then the NMOS transistor on the bottom pulls the output node down to ground (a logic 0). But if the input is a logic 0 (a low voltage) then the PMOS transistor on the top pulls the output node to Vdd (a logic 1).

Originally Posted by Athenian200

It looks like the the same idea as represented by the inversion circuit preceding it symbolically, but without the details of how it works.

Yup. That is the idea.

Originally Posted by Athenian200

All I can see is that somehow or other, Q3 takes the voltage-state of Input A into the circuit, Q4 takes the voltage-state of Input B into the circuit, and then their states are compared with what I assume are some kind of static positive voltage references in Q1 and Q2, which if met result in the current that normally causes the circuit to read as on being blocked/stifled. Is that it?

Not quite. For digital CMOS circuits like these you don't need to worry about references or voltage comparisons (very much). Just treat the transistors like switches.

Here are a couple of things to note:
In order to connect the output node to ground, you need both Q3 and Q4 to connect their respective drains to their sources. So you need both their inputs to be logic 1s.
In order to connect the output node to Vdd, either Q1 or Q2 or both to connect their respective drains to their sources. This happens when either (or both) of their inputs are logic 0s.

Originally Posted by Athenian200

Abstractly, the idea of an NAND gate seems to be similar to this:

If both conditions A and B are true, this statement is false. Otherwise, this statement is true.

That's the idea. Yes.

Originally Posted by Athenian200

So... is this thing attempting to implement logic in the form of an electronic circuit?

Yup. Until other means of computing become efficient, the logic is implemented electronically.

The thing about the NAND gate is that it is a "logically complete" set of gates by itself. That means you can implement all possible logical functions by just using 2 input NAND gates. You can make it into an inverter by connecting the inputs together and/or connecting one of the inputs to 1. You can create an AND function by inverting the output of the NAND gate(using the NAND as inverter). You can get an OR gate by inverting the inputs(using the NAND as inverter) to a NAND gate.

Originally Posted by Athenian200

It appears to be a representation of how the circuit works on an abstract level (two inputs and one output, with a body doing something with it), but without the details of how it works. It looks like a straightforward representation of it if you already know how it works.

Yes. Circuits can look really complicated without the use of symbols. Generally, we use a box with the inputs and outputs, with none of the internals as a symbol for generic circuits. So we'd have to actually look at the schematic for the symbol to understand what is going on. For standard circuits, like the inverter, NAND and others, there are standard sysmbols, so we don't use a box.

Originally Posted by Athenian200

I'm not sure I understand this exactly, but here's what it seems to be doing. If the blue lines are one state of the clock, and the red lines are the other... it seems as if the circuit is set up so that depending on which state the clock is in (red or blue), one part of whatever it is that started at D goes through to the end (and something happens to it) while the other is held in a loop of some kind. What goes through, and what is kept in a loop, seems to alternate between whether red or blue is the current state of the clock.

That is basically it (though it is more black vs. colored rather than red vs. blue). Can you see why what was on D gets transfered to the red transmission gate when the CL is low, and then transferred from the red transmission gate to the Q node when the CL is high?

Originally Posted by Athenian200

Does it have something to do with volatile memory needing to be constantly self-refreshed in order to avoid being wiped out?

It is volatile memory. But it is a "static" type. The feed-back loops in the latches keep the values stored (as long ad the circuit has power) even where there is no external circuit driving the D-input.
Refreshes (and "pre-charges") are usually associated with "dynamic" circuits, because in these the logic values are stored capacitively, not with the use of a static feedback loop.
This is also interesting stuff. But more in the realm of circuit design.

Originally Posted by Athenian200

Anyway, if the clock cycles frequently, it seems as if the circuit is set up so that all the stuff coming in at D can go through eventually, but ensures that only one thing at a time can do so.

That is the essential idea. The clock cycles on a periodic basis, and these flip-flops will be used in various parts of a circuit to synchronize other signals to the clock.

Originally Posted by Athenian200

I'm sorry I haven't been commenting as you've been writing... I tend to absorb passively, keep my thoughts to myself. I had some thoughts on your earlier posts, but I wasn't sure anyone would be interested. When I figured out that you were losing motivation because no one was commenting on it, I decided I should share some of my thoughts.

I like it when people make comments, that way I know where I am loosing people.

Originally Posted by Bear Warp

I'm still interested, ygolo. I've just been distracted with college stuff lately. I have plenty of time to look over your last two posts today, though.

Just let me get some coffee first...

That's cool. Hopefully, my responses to Athenian will help you as well.
I just wasn't sure since I was sick for a while, if people had just moved on.