[Athenian200]

Originally Posted by ygolo

I got rather ill today, so there will be a short break on the concrete examples since that takes a bit of concentration.

Though we don't want to go too far down the circuit design/device physics information (inceredibly intersting stuff in its own right), a certain amount needs to be understood before I specify an implimentation to our micro-architecture.

Although there are a lot of cicuit styles, the most popular one for a long-time is CMOS (Complementary Metal Oxide Semiconductor) technology. The reason for the popularity us due to the generally low power dissipation.

For our purposes, we can think of MOS transistors as simple switches. There are two types often refered to as NMOS, and PMOS.

The device physics is interesting and perhaps we can discuss it in another thread. Pictured below is the NMOS version.


Anyway, the MOS transistors are 4-terminal devices. They are called drain, gate, source, and bulk. For out purposes, we can consider the bulk terminals for the NMOS being connected to ground, and the PMOS bulk terminals connected to supply-voltage of the circuit.

What happens is when the appropriate voltage is applied to the gate terminals, the source and drain terminals become electically connected. It is actually more subtle than this, but we can save that for another thread.

So we can think of the NMOS and PMOS transistors in the following way:

When a high voltage is applied to the gate of an NMOS the source and drain become electrically connected.
When a low voltage is applied to the gate of an PMOS the source and drain become electrically connected.

One catch to this is that (due to particular voltage thresholds to keep the transistors on) NMOS's don't pass high-voltages well between drain and source, and PMOS's don't pass low voltages well.

For this reason, both versions need to be used in a complementary way. There is a lot that goes into the design of these circuits (its what I currently do for work) but for now I'll just show a few basic circuits (from which many other circuits can be built.

My first thought when reading this was, "Why do they need to have two kinds of gates that work in precisely opposite ways, instead of just one that can work either way?" But then I realized that they might need to do that because if they didn't, the state of the gate would be the same under either high or low voltage conditions, and would not have any effect on the circuit. Is that it?

First is a simpile inverter, which outpurs the inverted sense of the input. A 0 (low-voltage) input and creates a 1 (high-voltage) output, and vice-versa.


Please, see if you can see how the inversion function is implemented by this particular configuration of PMOS and NMOS.
The NMOS transistors have arrows going in to the bulks and/or no bubbles at the gates. The PMOS transistors have arrows going out of the bulk and/or bubbles at the gates.

The bulk just means the main part of the circuit, right? And the NMOS doesn't need bubbles because it's already connected to ground, but PMOS does because it's connected to the voltage? I'm guessing, here.

In order the keep more complex circuits looking less complicated, inverters tend to be replaced with the following symbol.

It looks like the the same idea as represented by the inversion circuit preceding it symbolically, but without the details of how it works.

Another important function (form which all other logical functions can theoretically be built) is a NAND gate.

If a, and b inputs are 1 (high-voltage) them the output is 0 (low-voltage). In all other cases(when the inputs are valid 1's and 0's), the output is 1 (high-voltage).

Please, see if you can see how the NAND function is implemented by this particular configuration.

All I can see is that somehow or other, Q3 takes the voltage-state of Input A into the circuit, Q4 takes the voltage-state of Input B into the circuit, and then their states are compared with what I assume are some kind of static positive voltage references in Q1 and Q2, which if met result in the current that normally causes the circuit to read as on being blocked/stifled. Is that it?

Abstractly, the idea of an NAND gate seems to be similar to this:

If both conditions A and B are true, this statement is false. Otherwise, this statement is true.

So... is this thing attempting to implement logic in the form of an electronic circuit?

Again, to make more complicated circuits more readable, the NAND gates are represented in schematics with a symbol like this:

It appears to be a representation of how the circuit works on an abstract level (two inputs and one output, with a body doing something with it), but without the details of how it works. It looks like a straightforward representation of it if you already know how it works.

So far, all the basic circuits I've mentioned have had no "memory." In order to make the flip-flops and other memory elements needed, we employ a little bit of positive feedback.

Here is a high-level schematic of a simple D-flip-flop:

The boxes with the lines in the center are called "transmission gates." They are composed of one PMOS and one NMOS in parallel. Notice that the inverted vesion of every signal that goes to transmission gate has the inverted version as well. That is because one is needed for the PMOS and the other for the NMOS.

There are two distiguishable states, "transparent" and "opaque." In the transparent state, the drains and sources are electrically connected. In the opaque state, the drains are elecrically issolated from the sources.

The end result is that the D input passes to the output when the CLK signal transitions from high to low. At all other times, there are positive feedback mechanisms that keep the output at the value it was last.

Please see if you can see this function from the confuguration.
Hint:The flip-flop is actually composed of two "latches." Each with its own set of tranmission gates and and feedback loop that are opaque or transparent based on the level of the clock.

I really suggest you spend some time puzzling out the basic circuits to see how they create the functions describes. I will answer questions if you get stuck. Once done, I dare say, you will have a much more knowledge than even "lay-people" even in other technichal fields (that is other than Electrical/Computer Engineering or Science).

I'm not sure I understand this exactly, but here's what it seems to be doing. If the blue lines are one state of the clock, and the red lines are the other... it seems as if the circuit is set up so that depending on which state the clock is in (red or blue), one part of whatever it is that started at D goes through to the end (and something happens to it) while the other is held in a loop of some kind. What goes through, and what is kept in a loop, seems to alternate between whether red or blue is the current state of the clock. Does it have something to do with volatile memory needing to be constantly self-refreshed in order to avoid being wiped out? Anyway, if the clock cycles frequently, it seems as if the circuit is set up so that all the stuff coming in at D can go through eventually, but ensures that only one thing at a time can do so.

I'm sorry I haven't been commenting as you've been writing... I tend to absorb passively, keep my thoughts to myself. I had some thoughts on your earlier posts, but I wasn't sure anyone would be interested. When I figured out that you were losing motivation because no one was commenting on it, I decided I should share some of my thoughts.