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ygolo · 08-25-2008, 01:21 AM

I had to fix some "bugs" in the micro-architecture before proceeding.
1) I changed opcode to opcode + constant. Making that bus 12 bits, instead of the 4 bits it originally was.
2) Added an 8-bit data-bus from execute unit to fetch/decode unit.

Hopefully, you could follow why I needed to make those changes. I'll leave it as an opportunity to the reader to test their understanding

So now, I'll show what happens on all of the buses, during a few cycles so that you get the gist of what is happening in the micro-architecture, as well.

First cycle:
Curr. PC Bus: 0x00
Instruction Bus:0x8000B
PAC Bus: (Addr:0, Source:0, Target 0)
RAC Bus: (Addr1:0,Source1:0,Target1:1,Addr2:0,Source2:0,Tar get2:0)
MAC Bus: (Addr:0,Source1:0,Target:0)
Op.Code+Constant Bus (OpCode:0x8, Constant: 0X0B)
Data Bus: 0x00
PRD Bus: 0x00
RRD Bus: 0x0000
MRD Bus: 0x00
PWD Bus: 0x00
RWD Bus: 0x0B
MWD Bus: 0x00
New PC Bus: 0x01

Second cycle:
Curr. PC Bus: 0x01
Instruction Bus:0x80101
PAC Bus: (Addr:0, Source:0, Target 0)
RAC Bus: (Addr1:1,Source1:0,Target1:1,Addr2:0,Source2:0,Tar get2:0)
MAC Bus: (Addr:0,Source1:0,Target:0)
Op.Code+Constant Bus (OpCode:0x8, Constant: 0X01)
Data Bus: 0x00
PRD Bus: 0x00
RRD Bus: 0x0000
MRD Bus: 0x00
PWD Bus: 0x00
RWD Bus: 0x01
MWD Bus: 0x00
New PC Bus: 0x02

Third cycle:
Curr. PC Bus: 0x02
Instruction Bus:0x30001
PAC Bus: (Addr:0, Source:0, Target 0)
RAC Bus: (Addr1:0,Source1:1,Target1:1,Addr2:1,Source2:1,Tar get2:0)
MAC Bus: (Addr:0,Source1:0,Target:0)
Op.Code+Constant Bus (OpCode:0x3, Constant: 0X01)
Data Bus: 0x00
PRD Bus: 0x00
RRD Bus: 0x0B01
MRD Bus: 0x00
PWD Bus: 0x00
RWD Bus: 0x0A
MWD Bus: 0x00
New PC Bus: 0x03

Fourth cycle:
Curr. PC Bus: 0x03
Instruction Bus:0xA0000
PAC Bus: (Addr:0, Source:0, Target 0)
RAC Bus: (Addr1:0,Source1:1,Target1:0,Addr2:0,Source2:1,Tar get2:0)
MAC Bus: (Addr:0xA,Source1:0,Target:1)
Op.Code+Constant Bus (OpCode:0xA, Constant: 0X00)
Data Bus: 0x0A
PRD Bus: 0x00
RRD Bus: 0x0A0A
MRD Bus: 0x00
PWD Bus: 0x00
RWD Bus: 0x0A
MWD Bus: 0x0A
New PC Bus: 0x04

Fifth cycle:

Curr. PC Bus: 0x04
Instruction Bus:0xC0000
PAC Bus: (Addr:0, Source:0, Target 1)
RAC Bus: (Addr1:0,Source1:0,Target1:0,Addr2:0,Source2:1,Tar get2:0)
MAC Bus: (Addr:0xA,Source1:0,Target:0)
Op.Code+Constant Bus (OpCode:0xC, Constant: 0X00)
Data Bus: 0x0A
PRD Bus: 0x00
RRD Bus: 0x0A0A
MRD Bus: 0x00
PWD Bus: 0x0A
RWD Bus: 0x0A
MWD Bus: 0x0A
New PC Bus: 0x05

The lines in red represent buses that changed in the current cycle. The lines in green the ones that changed at all.

08-25-2008, 01:21 AM	#21 (permalink)
ygolo My termites win Join Date: Aug 2007 Type: intp Location: North of somewhere (so not the south pole) Posts: 3,203	I had to fix some "bugs" in the micro-architecture before proceeding. 1) I changed opcode to opcode + constant. Making that bus 12 bits, instead of the 4 bits it originally was. 2) Added an 8-bit data-bus from execute unit to fetch/decode unit. Hopefully, you could follow why I needed to make those changes. I'll leave it as an opportunity to the reader to test their understanding So now, I'll show what happens on all of the buses, during a few cycles so that you get the gist of what is happening in the micro-architecture, as well. First cycle: Curr. PC Bus: 0x00 Instruction Bus:0x8000B PAC Bus: (Addr:0, Source:0, Target 0) RAC Bus: (Addr1:0,Source1:0,Target1:1,Addr2:0,Source2:0,Tar get2:0) MAC Bus: (Addr:0,Source1:0,Target:0) Op.Code+Constant Bus (OpCode:0x8, Constant: 0X0B) Data Bus: 0x00 PRD Bus: 0x00 RRD Bus: 0x0000 MRD Bus: 0x00 PWD Bus: 0x00 RWD Bus: 0x0B MWD Bus: 0x00 New PC Bus: 0x01 Second cycle: Curr. PC Bus: 0x01 Instruction Bus:0x80101 PAC Bus: (Addr:0, Source:0, Target 0) RAC Bus: (Addr1:1,Source1:0,Target1:1,Addr2:0,Source2:0,Tar get2:0) MAC Bus: (Addr:0,Source1:0,Target:0) Op.Code+Constant Bus (OpCode:0x8, Constant: 0X01) Data Bus: 0x00 PRD Bus: 0x00 RRD Bus: 0x0000 MRD Bus: 0x00 PWD Bus: 0x00 RWD Bus: 0x01 MWD Bus: 0x00 New PC Bus: 0x02 Third cycle: Curr. PC Bus: 0x02 Instruction Bus:0x30001 PAC Bus: (Addr:0, Source:0, Target 0) RAC Bus: (Addr1:0,Source1:1,Target1:1,Addr2:1,Source2:1,Tar get2:0) MAC Bus: (Addr:0,Source1:0,Target:0) Op.Code+Constant Bus (OpCode:0x3, Constant: 0X01) Data Bus: 0x00 PRD Bus: 0x00 RRD Bus: 0x0B01 MRD Bus: 0x00 PWD Bus: 0x00 RWD Bus: 0x0A MWD Bus: 0x00 New PC Bus: 0x03 Fourth cycle: Curr. PC Bus: 0x03 Instruction Bus:0xA0000 PAC Bus: (Addr:0, Source:0, Target 0) RAC Bus: (Addr1:0,Source1:1,Target1:0,Addr2:0,Source2:1,Tar get2:0) MAC Bus: (Addr:0xA,Source1:0,Target:1) Op.Code+Constant Bus (OpCode:0xA, Constant: 0X00) Data Bus: 0x0A PRD Bus: 0x00 RRD Bus: 0x0A0A MRD Bus: 0x00 PWD Bus: 0x00 RWD Bus: 0x0A MWD Bus: 0x0A New PC Bus: 0x04 Fifth cycle: Curr. PC Bus: 0x04 Instruction Bus:0xC0000 PAC Bus: (Addr:0, Source:0, Target 1) RAC Bus: (Addr1:0,Source1:0,Target1:0,Addr2:0,Source2:1,Tar get2:0) MAC Bus: (Addr:0xA,Source1:0,Target:0) Op.Code+Constant Bus (OpCode:0xC, Constant: 0X00) Data Bus: 0x0A PRD Bus: 0x00 RRD Bus: 0x0A0A MRD Bus: 0x00 PWD Bus: 0x0A RWD Bus: 0x0A MWD Bus: 0x0A New PC Bus: 0x05 The lines in red represent buses that changed in the current cycle. The lines in green the ones that changed at all. __________________ sloan+ Rxua\|I\|; primary Inquisitive; R(82%)L(52%)U(62%)A(54%)I(86%) CTO of IPTN (see Maverick's Sig.) and member of Maverick's Biker Club. Accept the past. Live for the present. Look forward to the future. My Blog I linked some of your blogs; if you feel that is inappropriate, please let me know.