OK. Either people have lost interest or there or no questions. I was expecting there to be some before I came back. Anyway, I'll do a short dump before I sign off.
I will be really surprised if there aren't questions after this, because we ought to be close to an implementable design of a microprocessor (an impractical one, though it may be) if I did things right. Note that this is a very crude implementation, more thought and care would be needed to make an optimal micro-architecture of the machine model presented earlier.
I'll include an attachment showing the block diagram of our little toy processor. (Note:I used a crude OpenOffice Draw package to do this, so the symbols are not standard)
There are going to be four blocks that are "clocked" by our cycle-clock, the Program Counter (PC), the memory, the register bank, and the ports. These four banks are indicated by those squiggly lines feeding them. What this means is that these blocks will hold on to their old values, till the next rising edge of our cycle clock, the they will accept the new values being fed to them.
The Code Space in our processor is clocked by the external programmer, and not the main cycle-clock.
The other two blocks are "logic" blocks, that don't have clocked elements. Based on the way I am using the buses (described soon), the fetch is trivial, and the decode is fairly straightforward also. The execute however does the brunt of the work, and may require a lot of explanation in a separate brain dump of its own.
Note, that the arrows in the diagram are "buses" or communication channels between the blocks.
The buses for the Memory, Ports and Registers, have three parts each. Each have an Address/Control Bus, a Read Data Bus, and a Write Data Bus. The Address/Control Buses are comprised of their respective addresses and more bits to indicate which are target and which are source (some are both). The Data Buses are as wide as to accommodate the most sources going to the Execute logic, and the targets coming from the execute unit.
We can view the Current PC as an "address" to the Code Space, and the instructions as the "data" coming from the code space.
So to Summarize the Buses:
Current PC Bus - 8-bits
New PC Bus- 8-bits
Instruction Bus- 20-bits
Port Address/Control (PAC) Bus - 3-bits, 1-bit port address, 1-bit indicating that it is source, 1-bit indicating that its target
Port Read Data (PRD) Bus - 8-bits
Port Write Data (PWD) Bus - 8-bits
Register Address/Control (RAC) Bus - 9-bits, two 2-bit register address, 2-bit indicating source, 1-bit indicating target
Register Read Data (RRD) Bus - 16-bits (2 8-bit source data potentially)
Register Write Data (RWD) Bus - 8-bits
Op.Code+Constant Bus - 12-bit, 4 bit opcode + 8-bit constant
Data-bus - for intermediate data, 8-bits
Now I am going to leave it up to questions (because I know there ought to be), before I explain further, to make sure I am not just being futile by posting.