[ygolo]

OK, so the programmer loads the following program into code-space:

0:0x8000B
1:0x80101
2:0x30001
3:0xA0000
4:0xC0000
5:0x10002
6:0x00000

This is the state of the registers (U=unknown):
PC:0x00
A :0xUU
B :0xUU
C :0xUU
D :0xUU

All the memory locations have unknown values, the 7-segment display is showing some random hex value, and the switches are irrelevant for this program.

All processors go through a cycle similar to the following:
1) Fetches the next instruction
2) Decodes the instruction
3) Executes the instruction

Modern machine are quite a bit more complicated in that they often fetch many instructions at a time use branch-prediction, often have multiple pipelines at various stages of execution, and have to have a way to "retire" the instructions in the correct order, but we'll stick to the simple version for a while.

First cycle:
Fetches, the following:
0:0x8000B

Decodes it to mean
Load Constant 0x0B into register 0 (i.e. Register A)

It then executes the instruction, yielding:
A :0x0B

Since the instruction was not a branch instruction, it auto-updates the PC.
PC : 0x01

Second cycle:
Fetches, the following:
1:0x80101

Decodes it to mean
Load Constant 0x01 into register 1 (i.e. Register B)

It then executes the instruction, yielding:
B :0x01

Since the instruction was not a branch instruction, it auto-updates the PC.
PC : 0x02

Third cycle:
Fetches, the following:
2:0x30001

Decodes it to mean
Subtract the value in register 1 (register B) from register 0 (Register A), and keep result in Register 0.

It then executes the instruction, yielding:
A :0x0A

Since the instruction was not a branch instruction, it auto-updates the PC.
PC : 0x03

Fourth cycle:
Fetches, the following:
3:0xA0000

Decodes it to mean:
Write memory addressed by register 0 (register A) the value in register 0 (Register A).

It then executes the instruction, yielding a change in memory location 0x0A:
0x0A :0x0A

Since the instruction was not a branch instruction, it auto-updates the PC.
PC : 0x04

Fifth cycle:
Fetches, the following:
4:0xC0000

Decodes it to mean:
Decodes it to mean output to port 0 (port IO_A) the value in register 0 (Register A).

It then executes the instruction, yielding a change to the seven segment display:
0x0A is displayed on the pair of 7-segment displays.

Since the instruction was not a branch instruction, it auto-updates the PC.
PC : 0x05

6th cycle:
Fetches, the following:
5:0x10002

Decodes it to mean:
If the value in register 0 (register A) is not zero, change the program counter to 0x02

It then executes the instruction:
Since the value in the register A is 0xA (therefore not zero), the program counter is changed.

PC:0x02

7th cycle:
Fetches, the following:
2:0x30001

Decodes it to mean
Subtract the value in register 1 (register B) from register 0 (Register A), and keep result in Register 0.

It then executes the instruction, yielding:
A :0x09

Since the instruction was not a branch instruction, it auto-updates the PC.
PC : 0x03

Note that this is the same as the 3rd cycle except the values are changed. The Eight through 10th are essentially repeats of 4rth through 10th as well. It will keep looping from PC value 0x02 through 0x05, that is till ...

46th cycle:
Fetches, the following:
5:0x10002

Decodes it to mean:
If the value in register 0 (register A) is not zero, change the program counter to 0x02

It then executes the instruction:
Since the value in the register A is 0x0, the program counter proceeds with its normal auto-update.

PC:0x06

47th cycle:
Fetches, the following:
6:0x00000

Decodes it to mean:
Halt the processor.

It then executes the instruction:
The processor execution is stopped.

Hopefully, the actual execution makes sense because, next, I plan to give some insight into the circuits that actually make this happen.

Also, if the pace is too slow, let me know. We haven't really gotten to the point at which we are talking about the types of decisions Computer (Micro-)Architects have to make. There is a lot of back-ground information needed.